General electric alternating-current (AC) power (“mains power” or “mains electricity”) may need to be converted into direct-current (DC) power for use by a multitude of consumer devices. A power management system can convert AC power from the main source into DC power using components such as, for example, inductors, diodes, capacitors, transformers and other switches (e.g., unction gate field-effect transistors, metal-oxide semiconductor field-effect transistors, etc.) with low losses in power dissipation. Losses in the main source may be decreased by focusing on the harmonics of the current drawn from the main source and the phase relationship between the mains voltage and the current drawn from the main source. The power factor of an AC to DC electric power system may be defined as the ratio of the real power drawn from the main source compared to the product of the root means square (rms) voltage ‘Vrms’ and the rms current ‘Irms’. The power factor therefore indicates how much more RMS (Root Mean Square) current can be taken from the mains compared to the optimum, and therefore indicates the losses in wires of the mains grid related to the optimum situation.
A power factor corrector (PFC), which may include a bridge rectifier, a switch-mode power supply (SMPS), and control circuits, can be used to help maximize the power factor in power management systems and can also be used for power management in personal computers, adapters, lighting and so on. A power factor can therefore function as a parameter used in evaluating the overall performance of a power factor corrector.
PFC circuits can be used in applications such as power converters to control the phase of the input current and help maximize power in power management systems. A power factor corrector (also referred to as “PFC circuit” or simply as a “PFC”) may be needed for a SMPS to operate with power levels above, for example, 75 watts. For a power level above approximately 300 watts, a CCM (Continuous-Conduction Mode) operation can become attractive because this can lead to the use of small EMI (Electromagnetic Interference) filters, which are useful in smaller electronic devices.
Traditional PFC circuits may use fixed frequency in CCM applications. Close to the main zero-crossing, however CCM may not be maintained, and a changeover from a BCM (Boundary Conduction Mode) to a (Discontinuous-Conduction Mode) DCM can occur in association with a rising frequency. Unfortunately, this feature can result in a lower efficiency close to the main zero-crossing.
For optimum efficiency, it may be advantageous to use CCM at higher power levels around the peak voltage of the main power supply and then use DCM in other situations.
Some DCM applications may employ a topology involving ‘Ton’ (‘On Time’) control for the PFC switch. ‘Ton’ control offers the advantage for BCM of automatically correcting the mains current shape for a high power factor. This is because di/dt=Vmains/Lind, wherein Lind is the main inductor value. Thus with a fixed ‘Ton’, the primary peak current is proportional to the momentary mains voltage. For CCM, the primary current may depend on the current at the end of the previous switching cycle and the switch conduction interval ‘Ton’. Therefore, on time control in the manner used in DCM cannot be employed in CCM operations.
Some CCM operational techniques may use a method referred to as “average current control”. This approach can be based on the fact that the duty cycle of the secondary stroke equals Vin/Vout where Vin can be the input voltage of the PFC and Vout can be the output voltage. FIG. 1 depicts a waveform diagram 100 illustrating the concept of average current control CCM as exemplified by waveforms 102, 104, and 106, and a ramp signal 108 and a control signal 110. The waveforms shown in the waveform diagram 100 of FIG. 1 demonstrate that when the duty cycle becomes smaller than an equilibrium value, the duration of the secondary stroke can also become smaller. This can offer less reduction for the inductor current and therefore an increase in the current as compared to the current at the start of the switching cycle (e.g., see waveform 102 in FIG. 1). This can be demonstrated by “duty_off<equilibrium→lav rises” as shown in FIG. 1, wherein “lav” can refer to an average inductor current and “duty_off” can refer to a duty cycle.
When the duty cycle is higher than the equilibrium, an increase in the reduction of the inductor current can occur, and therefore a corresponding decrease in the current can result, as compared to the current at the start of the switching cycle (e.g., see waveform 106 in FIG. 1). This can be demonstrated by “duty_off>equilibrium→lav falls” as shown in FIG. 1, wherein “lav” can refer to an average inductor current and “duty_off” can refer to a duty cycle.
The duty cycle may be generated by a ramp signal 108 (i.e. a “ramp” for PWM (Pulse Width Modulation)) and a control signal 110, where the ramp signal 108 and the control signal 110 can be then subjected to a comparison operation by a comparator that generates the duty cycle signal.
This means that an equilibrium may occur when the control signal 110 is proportional to Vin/Vout, wherein Vin represents an input voltage and Vout represents an output voltage. As the output voltage Vout can be normally regulated to a fixed value, the result can be that the control signal may be proportional to the input voltage Vin. By making the control signal 110 proportional to the sensed current, the system can generate an input current that may be proportional to the momentary mains voltage (Vmains(t)), which can fulfill a power factor requirement.
FIG. 2 depicts a schematic diagram of a PFC circuit 130 that can apply the average current control principle. The circuit 130 shown in FIG. 2 includes a pair of diodes 132, 134 and another pair of diodes 136, 138. The diodes 134 and 138 can connect to ground 140. An inductor 144 can connect to diodes 132 and 138, and can also connect to ground 140 and the output of the diode 132 and the diode 136.
The circuit 130 can further include an oscillator 146 that connects to the negative input of an amplifier 148 that can output PWM waveforms that can be supplied to a transistor 150. The inductor 144 can also connect to the transistor 150 and to a diode 152. An output capacitor 154 can connect to the output of the diode 152 and to ground 141. The output capacitor 154 can be electronically located between a ground output (“Out Gnd”) and the output of the diode 152.
The circuit 130 can further include a resistor 158 (“Rop”) that is coupled to a shunt resistor 156 (“Rshunt”), ground 140 and the diode 138 and the diode 134. The shunt resistor 156 can be further connected to a resistor 160, which in turn can be coupled to a capacitor 164 and to a current amplifier 162. The capacitor 164 can be further coupled to a capacitor 166 and to a resistor 168. The capacitor 166 and the resistor 168 can also connect to the output of the current amplifier 162. The capacitor 166 and the resistor 168 can be arranged in parallel with one another and can further connect to the positive input of the amplifier 148 and the output of the current amplifier 162. That is, the current amplifier output (i.e., output ‘Vca’) can connect to the positive input of the amplifier 148.
FIG. 3 depicts a schematic diagram of a control circuit 180 that can employ a multiplier approach. The control circuit 180 can include an voltage source 182 that can be offset by a diode 184. The voltage source 182 may be an AC voltage source and can supply an AC voltage ‘VAC’ to a resistor 186 (‘RIAC’) and to an inductor 212. The resistor 186 can be coupled to a multiplier 188 that in turn can connect to a resistor 190 and the positive input of an amplifier 192 whose output can connect to a latch 194. The latch 194 can also be coupled to a gate driver logic component 200 that can connect to a transistor 219.
A resistor 198 can further connect to the transistor 214 and to ground 196. The transistor 214 can be further coupled to the inductor 212 and to a diode 216. A capacitor 218 can connect to the diode 216 and to the resistor 198 (and also to ground 196). The capacitor 218 can be also be arranged in parallel with a load 220. A resistor 210 can connect to the capacitor 218 and to the diode 216 and a resistor 208 and also to the negative input of an error amplifier 202 that outputs a voltage VEA. The resistor 208 can also be coupled to ground 206. A reference voltage 204 (“VREF”) can connect to the positive input of the error amplifier 202. The output from the error amplifier 202 can also be coupled to the multiplier 188.
In control circuit 180, the control output VEA from the error amplifier 202 can set the power level in order to allow the PFC output voltage to be equal to the desired level while delivering power to the load 220. The multiplier 188 can then multiply the control output signal with the mains voltage shape to output a desired current level, which can be then compared with a sensed current level and can be further used to reset the latch 194 in order to define a primary current peak level. The switching cycle can be started by a ‘Zcd’ (zero current detection) signal in order maintain the system in a BCM.
For a system in BCM operation, the input current drawn from the mains can be proportional to the primary peak current and can also be proportional to the “on time” of the PFC switch. This arrangement can make it easy to render a good power factor. When the system goes to DCM, the average current may be lower for the same primary peak current, because of a ringing interval that may arise after the end of the secondary stroke where no current is drawn from the mains. Some devices may use a PFC circuit where this effect can be compensated by the additional adaption of the primary peak current based on the ratio: Tper/(Ton+Tsec).
FIG. 4 depicts a group of equations 230 that can be used to define factors for a PFC circuit. Providing for a high power factor means that the input current drawn by the PFC circuit can be proportional to the momentary mains voltage. Ideally, this situation can be represented by defining a factor K2 according to the equations 230 as shown in FIG. 4. That is:Iin=k2·VmainsPin=Vmains·IinPin=Vmains·(k2·Vmains)Pin=Vmains2·k2
Thus, the momentary input current equals the momentary mains voltage times a factor k2. This means that the momentary input power can be proportional to the square of the momentary input voltage.
FIG. 5 depicts a graph 240 and a graph 250 demonstrating power factor data for a power factor corrector according to the equations 230 shown in FIG. 4. Graph 240 and curve 242 plot data indicative of Vmains(t) with respect to time ‘t’ based on the equation Pin (t,K2):=Vmains(t)2·k2 wherein k2b:=0.002. Graph 250 depicts curves 252 and 254 respectively for Pin(t,k2b) and Pin (T,k2Aa) wherein k2a=1×10−3 and k2b=2×10−3. It should be appreciated that such values and parameters are illustrated and discussed herein for illustrative purposes only and are not limiting features of the disclosed embodiments.
FIG. 6 depicts a graph 260 depicting average power over a mains half cycle for a power factor corrector circuit. The curve 262 and the curve 264 shown in graph 260 demonstrate that for the average power over a mains half cycle, the average value of the power can be half of the peak value of the square of a sine wave:
      Pin_av    ⁢          (                        k          ⁢                                          ⁢          2                ,        Vmainspeak            )        =                              Vmainspeak          2                2            ·      k        ⁢                  ⁢    2  
Thus, fixing the value ‘k2’ would mean that the power level is proportional to the square of the mains voltage amplitude. Accordingly, the gain of the closed loop can be proportional to the square of the mains voltage amplitude. In some cases, it may be desirable to have a fixed gain of the total control loop. A constant gain can prevent a 0 db loop gain frequency for closed loop shifts. In this manner, an optimum dynamic response may be possible for universal mains voltage while maintaining optimum stability for the loop.
K2 therefore can include a mains voltage that is compensated by 1/Vmains{circumflex over ( )}2, which allows the gain from the control-to-output power to be compensated for the mains voltage amplitude.
In a practical PFC, it is not easy to define behavior according to this desired factor k2. Prior art DCM controllers, for example, often use on-time control with BCM or fixed frequency DCM. In BCM, the factor k2 may be more or less defined as a fixed-on-time factor, which can cause a peak current, ‘Ipeak’, to be proportional to the momentary mains voltage. Therefore in BCM, the input current can be proportional to “Ipeak/2’ and may be also proportional to the mains voltage. In DCM with fixed frequency, the average current is no longer ‘Ipeak/2’ because of the changing ratio between the ‘primary+secondary’ stroke and the period time.
With conventional techniques and circuits such as discussed above, it may be possible to configure a CCM or a DCM power factor corrector. To date, CCM and DCM approaches have not been combined in a manner that allows a power factor corrector to operate for DCM and CCM within the main half cycle. In addition, the loop gain and dynamic behavior are different in CCM and DCM applications in power factor correctors, which makes it more complex to define a closed loop and obtain a dynamic performance. Another problem with power factor correctors relates to potential instabilities (e.g., short long cycles) that can occur in CCM for a duty cycle greater than 50%. In addition, the operating frequency in BCM leads to undesired large frequencies during part of the mains half cycle.
Accordingly, there is a long-felt need for AC/DC power converters in power management systems to address the foregoing problems.